Note on using a terminal (Zterm) to transfere text files to amforth. 

amforth used ''rx0'' and ''tx0'' as ''key'' and ''emit''. ''rx0'' and ''tx0'' where interupt driven and worked with an input and output queue to provide a fast I/O. But this queues caused trouble in text pacing with some terminals when sending textfiles instead of typing manualy. Characters got lost and buffer overrun ocured.

The text pacing feature of Ztern - wait for character echo - worked best, when a simple key and emit mechanism was used that just polled the UASRT. This way the character echo done by ''accept'' had the funktion of a request for another character from terminal. There was no need to set a charcter delay time for the text pacing in terminal this way. 

This waiting for charcter echo includes control character ''cr'' (carriage return). As ''cr'' is not echoed by amforth until interpreting the terminal input buffer ''TIB'' is complete, terminal waits at the end of a line until amforth is ready to accept characters again. Compiling new words worked very well this way. (We remember: During compilation - i.e. writing the flash - the interupts have to be off, and turning them on again seemed to cause extra trouble with rx0 and tx0.)

So if you have trouble sending text to amforth, try this simple I/O.

<code>
; Simple USART I/O in amforth polling the UDR of USART. 


; USART funktions:

; USART I/O Data Register UDR 
; Write to UDR --> transmit character to terminal. 
; Read from UDR <-- recieve character send by terminal. 

; USART Control and Status Register A  UCSRA 
; Bit 7  RXC: USART Receive Complete 
; Bit 6  TXC: USART Transmit Complete 
; Bit 5  UDRE: USART Data Register Empty 
; Bit 4  FE: Frame Error 
; Bit 3  DOR: Data OverRun 
; Bit 2  UPE: USART Parity Error 
; Bit 1  U2X: Double the USART Transmission Speed 
; Bit 0  MPCM: Multi-processor Communication Mode 

; USART Control and Status Register B  UCSRB 
; Bit 7  RXCIE: RX Complete Interrupt Enable 
; Bit 6  TXCIE: TX Complete Interrupt Enable 
; Bit 5  UDRIE: USART Data Register Empty Interrupt Enable 
; Bit 4  RXEN: Receiver Enable 
; Bit 3  TXEN: Transmitter Enable 
; Bit 2  UCSZ2: Character Size 
; Bit 1  RXB8: Receive Data Bit 8 
; Bit 0  TXB8: Transmit Data Bit 8 

; USART Control and Status Register C  UCSRC 
; Bit 7 - nc 
; Bit 6  UMSEL: USART Mode Select 
; Bit 5:4  UPM1:0: Parity Mode 
; Bit 3  USBS: Stop Bit Select 
; Bit 2:1  UCSZ1:0: Character Size 
; Bit 0  UCPOL: Clock Polarity 

; USART Baud Rate Registers  BRRL and UBRRH

; bit ruler 
; %76543210 
;     11000 
;       110 


; ( -- v) System Value 
; R( -- ) 
; returns usart0 baudrate 
VE_BAUD0: 
  .db 05,"baud0" 
  .dw VE_HEAD 
  .set VE_HEAD = VE_BAUD0 
XT_BAUD0: 
  .dw PFA_DOVALUE 
PFA_BAUD00: 
  .dw 10 

; adjust settings to your needs. 
VE_USART0INIT:
    .db 10 ,"initusart0", 0 
    .dw VE_HEAD
    .set VE_HEAD = VE_USART0INIT
XT_USART0INIT:
    .dw DO_COLON 
PFA_USART0INIT:        ; ( -- ) 
    .dw XT_DOLITERAL
    .dw $18             ; $18 . 11000 ok 
    .dw XT_DOLITERAL 
    .dw UCSRB 
    .dw XT_CSTORE 
    .dw XT_DOLITERAL
    .dw $6              ; $6 . 110  ok 
    .dw XT_DOLITERAL 
    .dw UCSRC
    .dw XT_CSTORE 
    .dw XT_BAUD0        ; get sytem value from eeprom. 
    .dw XT_DUP 
    .dw XT_BYTESWAP 
    .dw XT_DOLITERAL 
    .dw UBRRH
    .dw XT_CSTORE 
    .dw XT_DOLITERAL 
    .dw UBRRL
    .dw XT_CSTORE 
    .dw XT_EXIT 


; Data register empty? UDRE=bit5 ) 
VE_DOEMITQ:
    .db 7 ,"doemit?" 
    .dw VE_HEAD
    .set VE_HEAD = VE_DOEMITQ
XT_DOEMITQ:
    .dw DO_COLON 
PFA_DOEMITQ:        ; ( -- f ) 
    .dw XT_DOLITERAL 
    .dw UCSRA 
    .dw XT_CFETCH 
    .dw XT_DOLITERAL 
    .dw $20 
    .dw XT_AND 
    .dw XT_EXIT 


VE_DOEMIT:
    .db $6 ,"doemit",0
    .dw VE_HEAD
    .set VE_HEAD = VE_DOEMIT
XT_DOEMIT:
    .dw DO_COLON 
PFA_DOEMIT:        ; ( c -- ) 
PFA_DOEMIT0:
    .dw XT_DOEMITQ
    .dw XT_DOCONDBRANCH
    .dw PFA_DOEMIT0 
    .dw XT_DOLITERAL 
    .dw UDR
    .dw XT_CSTORE 
    .dw XT_EXIT 


; Recieve comlplete? RXC=bit7 ) 
VE_DOKEYQ:
    .db 6 ,"dokey?",0
    .dw VE_HEAD
    .set VE_HEAD = VE_DOKEYQ
XT_DOKEYQ:
    .dw DO_COLON 
PFA_DOKEYQ:        ; ( -- f ) 
    .dw XT_DOLITERAL 
    .dw UCSRA
    .dw XT_CFETCH 
    .dw XT_DOLITERAL
    .dw $80 
    .dw XT_AND 
    .dw XT_EXIT 


VE_DOKEY:
    .db $5 ,"dokey"
    .dw VE_HEAD
    .set VE_HEAD = VE_DOKEY
XT_DOKEY:
    .dw DO_COLON 
PFA_DOKEY:        ; ( -- c ) 
PFA_DOKEY0:
    .dw XT_DOKEYQ             ; begin 
    .dw XT_DOCONDBRANCH
    .dw PFA_DOKEY0          ; until 
PFA_UDRFETCH:        ; ( -- c ) 
    .dw XT_DOLITERAL 
    .dw UCSRA   ; Must be read *bevor* udr, else not valid. 
    .dw XT_CFETCH 
    .dw XT_DOLITERAL 
    .dw UDR
    .dw XT_CFETCH 
    .dw XT_SWAP 
    .dw XT_DOLITERAL
    .dw $8 
    .dw XT_AND         ; Data overrun bit set? DOR=bit3  
    .dw XT_DOCONDBRANCH
    .dw PFA_UDRFETCH0 
    .dw XT_DOLITERAL
    .dw $80 
    .dw XT_OR        ; Set bit7 in char to indicate DOR.  
PFA_UDRFETCH0:  
    .dw XT_EXIT 


; ' DOKEY  is key 
; ' DOEMIT is emit 
; ' DOKEYQ is key? 
; ' NOOP   is /key 

; ( -- ) Hardware Access
; R( --)
; set teriminal i/o vectors 
VE_SET_TERMINAL_VECTORS:
  .db 6, "set-tv", 0
  .dw VE_HEAD
  .set VE_HEAD = VE_SET_TERMINAL_VECTORS
XT_SET_TERMINAL_VECTORS:
  .dw DO_COLON
PFA_SET_TERMINAL_VECTORS:          ; ( -- )
  
  .dw XT_DOLITERAL
  .dw XT_DOEMIT
  .dw XT_DOLITERAL
  .dw XT_EMIT
  .dw XT_DEFERSTORE

  .dw XT_DOLITERAL
  .dw XT_DOEMITQ
  .dw XT_DOLITERAL
  .dw XT_EMITQ
  .dw XT_DEFERSTORE

  .dw XT_DOLITERAL
  .dw XT_DOKEY
  .dw XT_DOLITERAL
  .dw XT_KEY
  .dw XT_DEFERSTORE

  .dw XT_DOLITERAL
  .dw XT_DOKEYQ
  .dw XT_DOLITERAL
  .dw XT_KEYQ
  .dw XT_DEFERSTORE

  .dw XT_DOLITERAL
  .dw XT_NOOP
  .dw XT_DOLITERAL
  .dw XT_SLASHKEY
  .dw XT_DEFERSTORE

  .dw XT_EXIT
; finis 
</code>