en:pfw:tasto
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| en:pfw:tasto [2025-06-22 00:26] – gelöscht - Externe Bearbeitung (Unbekanntes Datum) 127.0.0.1 | en:pfw:tasto [2025-08-04 11:28] (current) – [Forth implementation (noForth)] CC dazu mka | ||
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| + | ====== TASTO? ====== | ||
| + | |||
| + | A key (Italian tasto, Latin clavis) or a button is a control element that is operated by pressing and automatically returns to its original position when released. | ||
| + | |||
| + | Forth has '' | ||
| + | |||
| + | {{: | ||
| + | |||
| + | At [[en: | ||
| + | |||
| + | |||
| + | ===== Implementation for MSP430G2553 ===== | ||
| + | |||
| + | Here, the button is connected to pin 7 of port 1 of the MSP430G2553 microprocessor MCU. See circuit diagram in code. | ||
| + | |||
| + | |||
| + | ==== I/O ==== | ||
| + | |||
| + | This circuit provides a digital input, with the pin itself being the voltage source. | ||
| + | |||
| + | |||
| + | ==== Pseudo code ==== | ||
| + | |||
| + | < | ||
| + | Function: | ||
| + | | ||
| + | Function: | ||
| + | check digital voltage level | ||
| + | </ | ||
| + | |||
| + | |||
| + | ==== Forth implementation (noForth) ==== | ||
| + | |||
| + | The port pins are configured using registers. | ||
| + | The configuration register table is specified in the code. | ||
| + | The interrupt register indicates whether a falling edge was present. | ||
| + | |||
| + | In the direction register, P1.7 is set to digital IN. | ||
| + | The integrated **pull-up resistor is activated** to support the high level. | ||
| + | No interrupt should occur, so it is disabled. | ||
| + | The pin is used in the I/O function. | ||
| + | |||
| + | Try more or fewer than five queries to eliminate the bouncing. (More on the [[pfw: | ||
| + | |||
| + | < | ||
| + | \ test button | ||
| + | \ TI MSP430G2553 Launchpad with noForth mv 2553 240101 | ||
| + | \ CC by Michael Kalus, 20250804 | ||
| + | |||
| + | (* | ||
| + | History | ||
| + | 20250609 P1.7 digital input | ||
| + | |||
| + | addr acronym registername | ||
| + | 020 P1IN Input | ||
| + | 021 P1OUT | ||
| + | 022 P1DIR | ||
| + | 023 P1IFG | ||
| + | 024 P1IES | ||
| + | 025 P1IE Interrupt Enable | ||
| + | 026 P1SEL Port Select | ||
| + | 041 P1SEL2 | ||
| + | 027 P1REN | ||
| + | |||
| + | | ||
| + | R=47K | ||
| + | *) | ||
| + | |||
| + | hex | ||
| + | |||
| + | 80 constant pin7 \ mask for pin7 of port | ||
| + | |||
| + | : PININ ( mask -- ) \ make pin to input | ||
| + | ( 020 ) \ P1IN Input, read only | ||
| + | dup 021 *bis \ P1OUT | ||
| + | dup 022 *bic \ P1DIR | ||
| + | dup 023 *bic \ P1IFG | ||
| + | dup 024 *bic \ P1IES | ||
| + | dup 025 *bic \ P1IE Interrupt Enable, off | ||
| + | dup 026 *bic \ P1SEL Port Select, | ||
| + | dup 041 *bic \ P1SEL2 | ||
| + | 027 *bis \ P1REN | ||
| + | ; | ||
| + | | ||
| + | |||
| + | : TASTO? ( mask -- f ) \ Query button. debounced | ||
| + | >r | ||
| + | r@ 020 bit* 3 ms | ||
| + | r@ 020 bit* 3 ms | ||
| + | and | ||
| + | r@ 020 bit* 3 ms | ||
| + | and | ||
| + | r@ 020 bit* 3 ms | ||
| + | and | ||
| + | r@ 020 bit* 3 ms | ||
| + | and | ||
| + | r> = | ||
| + | ; | ||
| + | |||
| + | \ test mk | ||
| + | : tt ( -- ) | ||
| + | pin7 pinin | ||
| + | begin ( 100 ms ) \ add more ms if you like | ||
| + | pin7 tasto? . | ||
| + | key? until | ||
| + | ; | ||
| + | |||
| + | shield nn\ | ||
| + | freeze | ||
| + | ( finis) | ||
| + | </ | ||
| + | |||
| + | ==== Background information ==== | ||
| + | |||
| + | You can find them there: [[en: | ||
| + | |||
| + | |||
| + | ===== Contributions ===== | ||
| + | |||
| + | |||
| + | ===== Alternative Implementations ===== | ||
| + | |||
| + | You have another approach? | ||
| + | |||
| + | Please add it at the end of this document. | ||
| + | |||
| + | Sign in to post a comment. | ||